The present invention generally relates to the placement of cells in a circuit. More specifically, the present invention relates to a design methodology for cell placement in a circuit with shared inputs or outputs.
A typical standard cell outline has a rectangular shape. The rectangular cells are typically placed in a cell row. The cells can abut with each other on the cell row to minimize area. Currently, cell outlines are being redesigned and can have cell boundary shapes that are rectilinear polygons. For example, a cell boundary shape for one particular type of cell can be an “L” shape. This presents a challenge in achieving efficient cell placement that optimizes available area of a row.